1. Field of the Invention
The present invention relates to an electronic package structure and method for making the same. More particularly, the present invention relates to a three-dimensional stack electronic package structure and method for making the same by using a flexible substrate.
2. Description of Related Art
In recent years, demands for high-speed and large-capacity electronic products have significantly increased, and correspondingly, fabrication difficulties have increased too. Taking the memory among the electronic products as an example, the fabrication process has gradually become increasingly difficult as it developed from the early 4M, 16M and 64M to the contemporary 128M DDR or 256M DDR. Correspondingly, the chip yield of a single-die memory chip having large capacity is decreased. Hence, the large capacity memory can be achieved by improving the package fashion. For example, a 256M memory can be obtained by packaging two 128M chips in a three-dimensional stack manner. Not only can the complexity of the wafer fabricating process be significantly reduced but also the fabrication cost can be greatly reduced by the three-dimensional stack package.
In a common prior art, a single chip is packaged basically in accordance with a single-chip micro ball grid array as shown in FIGS. 1a and 1b. In the single-chip micro ball grid array, a main substrate 100 has a plurality of chips 150 mounted thereon. Also, the chip 150 has a plurality of fastening structures 170 so that electric signals from the chips are delivered to the main substrate 100 through the fastening structures 170 by weld joint, glue joint, hot joining or a combination thereof. If an increase of the capacity of the entire memory on the substrate is desired so as to result in a multichip micro electronic package structure having a plurality of units, more costs or more complex semiconductor chip fabricating technology will be involved. Oppositely, if the multichip package is used, it will merely require the lower-cost and matured semiconductor fabricating technology to obtain the higher yield. Furthermore, the memory capacity is increased to at least double to meet with the market demands.
In the multichip package, there are mainly plane/side-by-side juxtaposed multichip packages and stacked multichip packages. The plane/side-by-side juxtaposed multichip package using two or more than two juxtaposed chips is exemplified by U.S. Pat. No. 5,352,632, entitled “Multichip packaged semiconductor device and method for manufacturing the same”, which disclosed a connection of metal lead patterns between chips supported by a flexible resin tape to be sealed into a resin package. The tape adheres to the meal leads projecting from the package for being used in the known surface mount technology. In addition, U.S. Pat. No. 5,373,188, entitled “Packaged semiconductor device including multiple semiconductor chips and cross-over lead”, disclosed chips of different types connected to bonding pads of a chip of a lead frame, in which input/output terminals are wire bonded to inner leads of the lead frame. Furthermore, the leads are used above or below a semiconductor chip for connection to electrodes that are unable to be reached by cross-over leads. Finally, this assembly is encapsulated in a plastic package, resulting in a large-sized final product. The aforesaid two patents use the resin package to encapsulate multiple chips. Thus, it is difficult to rework a single damaged chip in the multichip package by replacement with an effective chip, and the entire multichip package has to be discarded. Hence, such packaging styles significantly increase fabrication cost.
In the multichip stack package, U.S. Pat. No. 4,862,322, entitled “Double electronic device structure having beam leads solderlessly bonded between contact locations on each device and projecting outwardly from therebetween”, disclosed a structure composed of two chips facing each other in which input/output terminals are connected by means of beam leads. Even so, the costs of the material, fabrication and control as associated with this beam lead technology are high, which prevents the package structure from being applicable to mass production. R.O.C. Pat. Pub. No. 506,101, entitled “Stackable flex circuit chip package and method of making the same”, disclosed a stackable integrated circuit chip package. This invention consists of a flex circuit, and also, multiple chips are packaged. Although this invention uses a three-dimensional stackable package capable of greatly reducing the entire volume of the package, such an electronic package structure adopts a conductive plastic body to package multiple chip sets. Hence, rework cannot be performed for a single damaged chip under the premise of cost control. R.O.C. Pat. Application No. 200303607, entitled “Stack-type chip semiconductor device”, disclosed a three-dimensional stack-type package having electric signals of chips stacked in a three-dimensional manner delivered to a carrier base by a wire bond, the stack chips being stuck together with glue interposed therebetween. Since input/output terminals of the chips on a semiconductor according to the prior ROC patent application do not locate around the chips, it is difficult to achieve a connection by the wire bond.
In the aforesaid electronic package assembly, differences in temperature distribution and coefficient of thermal expansion will cause thermal stresses to be mismatched in the interface area between different materials, and will even possibly cause damage to components as a result of electrode pad breakage or malfunction of a single die as a result of other reasons during the packaging process. As such, the entire package assembly is discarded. This kind of damage relates generally to fatigue rupture which is the primary cause resulting in a damaged electronic package component. It is therefore an important subject for the electronic package to come up with a way of how to extend the life of usage for an electronic component or how to replace a single die in a stack.
In view of the fact that the three-dimensional stack packaging technology will be used for the electronic-structure module of the electronic logic components and the electronic memory components to reduce the costs, minimize the package size and ensure capability of reworking the electronic package, the present invention provides an electronic package structure using a flexible substrate so as to greatly reduce fabrication cost of the stack electronic package and maintain the reliability after long term usage.
Therefore, it is desirable to provide an improved three-dimensional multichip stack electronic package structure to mitigate and/or obviate the aforementioned problems.